PANDA DAQT and FrontEnd Electronics Workshop, Rauischholzhausen Castle

The MVD silicon pixel detector readout architecture will be described. Special emphasis will be put on the full custom ASIC development for the front-end electronic.

Report on the IHEP Protvino group forward shashlyk readout electronics activity: photodetector selection, monitoring system test, PMT HV control.

Presentation of the first PWO matrix measurements with ASIC readout.

A summary of the Orsay meeting on the PANDA EMC electronics will be presented. We will go through the VFE implemented in the cold part and discuss the outlines of the digitization and concentration, the so-called "Multiplexing stage". We will try to give some ideas about the integration of this electronics within the Calorimeter Barrel. We will briefly present the prototypes under development and their associated tests. At the end, we will try to summarize the most relevant pending questions.

The feature-extraction algorithms for the EMC will be presented. During the presentation I will discuss digital filtering used for the signal processing, which resolution can be achieved by the EMC and what the resolution degradation at high rates.

A protoype of the PANDAbarrel DIRC was tested wit a proton beam in September 2009. The readout of the 256 MCP-PMT channels were done with HADES Trigger Readout Boards (TRP) and NINO discriminator boards as addons. The results and experience from this beam times will be presented.

The ongoing investigation of the particle identification using dE/dx method. with STT setup together with resulting requirements for front-end electronics will be presented..

Time to Digital Converters (TDCs) are widely used in many scientific applications. At GSI high-resolution ASIC-TDCs and commercial modules will be utilized in Time-of-Flight detectors for the upcoming FAIR experiments. The time-stretching methods used in high-resolution applications, e.g. the Vernier and the tapped delay lines (TDL) method, have also been successfully implemented in FPGA-Technology. The best recently known implementation achieves a RMS of 10 picoseconds (ps) with a reduced number of channels and an increased dead time in an Altera-FPGA. The advantage of a FPGA implementation is the less expensive and less time consuming design process as well as the flexibility and adaptability of the FPGA-TDC design to special needs of the current application. These facts motivated us to explore the achievable performance of a TDC implementation in a FPGA. We implemented a 32-channel, low dead time TDC based on the TDL method in a Virtex-4 FPGA. In this method standard chain structures in a FPGA – the carry chains – are used as a delay chain for time stretching purposes. The achievable time-resolution of the interpolation is determined by the intrinsic delay of a cell in the chain. In our implementation we used special techniques to improve the time resolution of the TDC beyond its cell delay. The TDC was tested by measuring the time between rising edges of the original and the delayed signal on different TDC channels. We measured delays in the range from 40 ps to 1 us. At small delays 9 ps RMS was achieved, additional 2 ps were induced by the limited accuracy of the system clock at 1 us delay. Thus the achieved resolution of a TDC channel is 6 ps (9/√2). Additional measurements were performed to characterize the influence of the temperature and supply voltage variations on the measured RMS value. The results of these measurements and the architecture of the FPGA-TDC will be presented.

This talk will give a brief information concerning the status of the GET4 TDC developement.

96-channel ADC board based on 10-bit 50 MSPS AD9212 chip will be presented. The board is one of the "AddOn" series for the TRB board and is used to collect data from the Shower detector at HADES experiment. The board provides Gb Ethernet output and can export data using UDP datagrams.

Up to now the digitisation part of the FEE and DAQ chain should be realised with COTS components. Espcially for the EMC readout where the digitisation unit has to be placed inside the magnet an application specific highly integrated solution would have some advatages. In this talk the concept for the HitDetection ASIC will be presented. The HitDetection ASIC is a self triggered transient recoder and digitiser well fitted to the needs of the PANDA readout.

In february the tape out of the third iteration of the APFEL preamplifier and shaper ASIC took place. From early summer 200 ASICs will be available for detector tests. So from the ASIC designers point of view the development is completed. We now need to decide which tests have to be integrated into a design readyness review and how much time will be spend on these tests. After the design readyness review there are stil several upcoming steps including production, testing and assembly. The talk will give an overview of the tests foreseen to be done by our group and the upcoming steps and its time requirements. In the end the project time schedule will be discussed.

Because of the complexity and the high startup cost of ATCA, initial PANDA DAQ development activities in Forschungszentrum Juelich concentrate on MicroTCA. MicroTCA provides a smooth path to ATCA, since MicroTCA boards can be reused in ATCA shelves by means of AMC carriers and all essential technological challenges, e.g. Management and high speed serial communication links on the backplane, can be studied in MicroTCA systems, too. As a starting point a multivendor system of crates, MCHs, CPUs and peripheral boards from several companies was set up in oder to establish a development platform and in order to investigate functionality and interoperability issues. The talk presents first experiences with MicroTCA and reports on the status of the ongoing AMC module developments.

An ATCA telecommunication shelf provides power, cooling and high-speed interconnections to up to 14 PANDA Compute Nodes. A single Shelf Manager supervises the installed boards and regulates the power distribution and temperature inside the shelf. The Shelf Manager relies on a local controller on each Compute Node to relay sensor alerts, provide hardware information and power requirements etc. An IPM Controller based on an Atmel microcontroller was designed for this purpose, and a prototype was produced. The neccessary firmware is being developed to allow local communication with the components of the Compute Node and remote communication with the Shelf Manager conform to the ATCA specification. An overview of the intended functions of the IPM Controller and a status report will be given.

Few options for implementation of serial links are presented. One option is based on FPGA built-in serial links and another one is a current CERN development of radiation hard serial link called GBT. Proposal for PANDA serial link protocols is presented.

The PANDA detector is a general purposed hadron spectrum planed to operate at the FAIR facility in Darmstadt, Germany. The PANDA EMC detector provides almost 4pi spatial coverage, good granularity and high energy resolution. A novel self-trigger data push data architecture for the PANDA data acquisition system requiring the data from EMC readout electronics to be processed on the fly to reconstruct electromagnetic shower. Features extracted from the electromagnetic shower combines with information from other detectors such as tracking and Cherenkov detectors in order to discriminate between photons, electron and hadrons. An EMC trigger and data acquisition scheme is proposed employing an FPGA based Compute Node (CN). The CN provides flexible connection with high bandwidth between processing modules, up to 10GByte DDR2 memory per board for data buffering and five high end FPGAs for sophisticated algorithm applications. A cluster finding algorithm is presented. The cluster finder also searches bumps in one cluster and distinguishes overlapped clusters which is essential for π0 reconstruction in high momentum and high luminosity experiments. Its energy and spatial resolution is measured. The cluster finding efficiency is studied based on simulation data. Some electromagnetic shower feature extraction algorithms which are usually done in offline trigger and their computing power requirements for FPGA implementation are discussed. The algorithms partition strategy, based on the readout electronics layout and the Compute Node based processing architecture, is also coved in the last part.

An online track finder for the PANDA experiment at the future FAIR facility was developed and tested. The central Panda tracking detectors for charged particles will consist of a silicon based micro vertex detector (MVD, 5-7 hits/track) and possibly of a straw tube tracker (STT, 15 double layers of straws). Due to the solenoidal magnetic field, tracks of charged particles can be parametrized by a helix (if neglecting energy loss). The algorithm works in several steps. Perpendicular to the beam direction the projection of the tracks is equivalent to a circle. Thus, first a conformal transformation will be used to convert the circles to straight lines. Second, a Hough transform is used to find the straight lines by a peak finding algorithm. Along the beam direction, a different Hough transformation is used. A peak finder returns all needed parameters to describe the helix track. As the algorithm was developed for an FPGA, it uses lookup tables. Results with simulations will be presented. Possible FPGA implementation will be discussed.

DIRC detectors in the PANDA experiment will give a high photon hit rate. Be it the current algorithms or new ones, they need to be adapted to run on the FFE systems and optimised for speed. And as the mechanical designs are not yet frozen, some minor changes that do not affect the detector performance may significantly ease the burden on the compute nodes.

Partial Reconfiguration (PR) offers the possibility to adaptively change part of the FPGA design without stopping the remaining system. Based on PR technology, we present a comprehensive framework for adaptive computing, in which design key points of hardware processes, system interconnections, Operating Systems (OS), device drivers, scheduler software as well as context switching are respectively concerned in different hardware/software layers. Technical perspectives are analyzed and it is foreseen to obtain great benefits with the proposed design framework for DAQ and triggering in nuclear and particle physics experiments.

The use of graphics processor units (GPUs) for event reconstruction in FairRoot will be presented. CUDA (Nvidia’s Compute Unified Device Architecture) development tools are in use for few months now. New features and technologies has arrived at the market from NVIDIA itself (pinned memory) and others companies (OpenCL). In this work, the use of some of these features, pro and contras will be presented.

Implementation of Gigabit Ethernet on TRB Addon boards is a cheap and efficient way to transport large amount of data from front-end electronics to event builders, and is a solution already used and being tested in HADES experiment in GSI, Darmstadt. The process of gathering data, constructing packets and finally transport them will be covered by my presentation.

The COMPASS experiment at CERN-SPS performed during the 2009 run a measurement of the Primakoff effect. This effect is characterized by high energetic photons in forward direction, which due to a very small angle respectively to the incident beam direction hit only the Electromagnetic Calorimeter in the second spectrometer stage(ECAL2). In order to efficiently detect those events the ECAL2 digital trigger system was developed. The trigger logic was integrated into the existing readout electronics, taking advantage of the flexible FPGA based sampling ADC modules, employed in the COMPASS experiment. The logic combined 512 calorimeter cells and calculated the total energy at every point of time on a bases of extracted signal amplitudes and temporal information. The single channel time resolution was measured to be in the order of 1 ns. The digital realization of the trigger logic allows to correct the time as well as the energy response of every calorimeter channel, and to monitor the system parameters. For the Primakoff run the trigger logic was configured to process 132 central calorimeter cells to identify events where the energy exceeds 50 GeV/c and 70 GeV/c. The 50GeV/c trigger was prescaled by a factor of 2 while all events with more than 70GeV/c were acquired. The total trigger rate was about 30 kHz. In this talk the functionality of the system as well as the system performance during the Primakoff run in 2009 will be presented.