Speaker
Description
The readout electronics chain of the LHCb RICH sub-detectors will be upgraded during LS3 Enhancements program scheduled for the 3rd LHC long shutdown. A novel front-end application-specific integrated circuit (ASIC) has been custom designed as the main core of the future RICH readout electronics. The FastRICH is implemented by using TSMC’s 65 nm CMOS technology node together with several radiation hardness techniques including triplication for the digital logic. It provides sensor-agnostic readout capabilities, which are tunned according to the RICH specifications and would allow timing measurements with several picosecond precision. The ASIC has been designed to meet the requirements for the 4th LHC RUN, as well as for the 5th and 6th during HL-LHC phase, when the LHCb will operate as a 4D-precision spectrometer. Large efforts are dedicated to prepare the testing and a validation campaign. This work presents the design of the new opto-electronics chain for the RICH LS3 Enhancement, the testbeam campaigns performed to validate the new concept, the validation setup and the testing routines which were prepared for the FastRICH prototype validation. The plan for the radiation campaign, with ions and X-rays during this fall, and ultimately a comprehensive radiation testing at the CHARM facility at CERN will be presented as well.
