14.–17. Apr. 2010
Rauischholzhausen Castle, Germany
Europe/Berlin Zeitzone

Sitzung

FEE Development II

15.04.2010, 09:00
Rauischholzhausen Castle, Germany

Rauischholzhausen Castle, Germany

http://www.uni-giessen.de/uni/einrichtungen/Rauischholzhausen/about.html

Präsentationsmaterialien

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  1. Eugen Bayer (Johann Wolfgang Goethe - Universität)
    15.04.10, 09:00
    Front End Electronics
    Time to Digital Converters (TDCs) are widely used in many scientific applications. At GSI high-resolution ASIC-TDCs and commercial modules will be utilized in Time-of-Flight detectors for the upcoming FAIR experiments. The time-stretching methods used in high-resolution applications, e.g. the Vernier and the tapped delay lines (TDL) method, have also been successfully implemented in...
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  2. Herr Harald Deppe (GSI Darmstadt)
    15.04.10, 09:30
    Front End Electronics
    This talk will give a brief information concerning the status of the GET4 TDC developement.
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  3. Dr. Krzysztof Korcyl (IFJ PAN)
    15.04.10, 10:00
    Front End Electronics
    96-channel ADC board based on 10-bit 50 MSPS AD9212 chip will be presented. The board is one of the "AddOn" series for the TRB board and is used to collect data from the Shower detector at HADES experiment. The board provides Gb Ethernet output and can export data using UDP datagrams.
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  4. Dr. Holger Flemming (Gesellschaft für Schwerionenforschung)
    15.04.10, 11:00
    Front End Electronics
    Up to now the digitisation part of the FEE and DAQ chain should be realised with COTS components. Espcially for the EMC readout where the digitisation unit has to be placed inside the magnet an application specific highly integrated solution would have some advatages. In this talk the concept for the HitDetection ASIC will be presented. The HitDetection ASIC is a self triggered transient...
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  5. Dr. Holger Flemming (Gesellschaft für Schwerionenforschung)
    15.04.10, 11:30
    Front End Electronics
    In february the tape out of the third iteration of the APFEL preamplifier and shaper ASIC took place. From early summer 200 ASICs will be available for detector tests. So from the ASIC designers point of view the development is completed. We now need to decide which tests have to be integrated into a design readyness review and how much time will be spend on these tests. After the design...
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