9.–12. Feb. 2010
GSI Helmholtzzentrum für Schwerionenforschung GmbH
Europe/Berlin Zeitzone

Sitzung

Gas systems and ageing (II) and digital systems

session 12
12.02.2010, 11:30
Hörsaal GSI (GSI Helmholtzzentrum für Schwerionenforschung GmbH)

Hörsaal GSI

GSI Helmholtzzentrum für Schwerionenforschung GmbH

Planckstr. 1 64291 Darmstadt Germany

Präsentationsmaterialien

Es gibt derzeit keine Materialien.

  1. Herr Suresh Kalmani (TIFR, Mumbai)
    12.02.10, 11:30
    An open loop gas recovery and recirculation system has been developed for the INO RPC system. The gas gas mixture coming from RPC exhaust is first desiccated by passing through molecular sieve (3Å + 4Å). Subsequent srubbing over basic active alumina removes toxic and acidic contaminants. The Isobutane and Freon are then separated by diffusion and liquefied by fractional condensation by cooling...
    Go to contribution page
  2. Herr Marek Palka (Universität Frankfurt)
    12.02.10, 11:50
    The concept of a general purpose Trigger Readout Board (TRB) had its source in the future needs of the HADES (High Acceptance Di-Electron Spectrometer). The HADES is a running experiment, installed at the SIS-18 synchrotron (GSI, Germany). Next years HADES will be moved to the upcoming FAIR accelerator complex. Here, HADES-at-FAIR will continue its experimental program. Due to mentioned plans,...
    Go to contribution page
  3. Dr. Holger Flemming (GSI Darmstadt)
    12.02.10, 12:10
    In 2005 the GSI ASIC design group started with an evaluation of different TDC core architectures for a high resolution TDC for the CBM Time of Flight detector. Based on this evaluation a high resolution TDC fitting to the ambitious requirements of the CBM experiment was developed. Now with the GSI Eventdriven TDC with 4 channels (GET4) ASIC a prototype is available with a time resolution of...
    Go to contribution page
  4. Dr. Zhi Deng (Tsinghua University, Beijing)
    12.02.10, 12:30
    High resolution readout electronics is under development for MRPC detectors. It consists of a fast front‐end ASIC and an ultra high resolution TDC based on FPGA. The front‐end ASIC, CAD (Current Amplifier and Discriminator), works in fully current mode. Signal pulses are amplified by a current mirror with local negative feedback to reduce the input impedance and then are sent to a current...
    Go to contribution page
  5. 12.02.10, 12:50
Erstelle Zeitplan ...