Name: Joint CBM / Panda DAQ developments - "Kick-off" meeting
Start: 2015-02-19T12:30:00+01:00
End: 2015-02-20T15:00:00+01:00
Location: GSI

Joint CBM / Panda DAQ developments - "Kick-off" meeting

from Thursday, 19 February 2015 (12:30) to Friday, 20 February 2015 (15:00)

Monday, 16 February 2015
Tuesday, 17 February 2015
Wednesday, 18 February 2015
Thursday, 19 February 2015
13:00
13:00 - 14:45
Room: KBW small lecture hall
Contributions

13:00 Introduction

13:15 Panda DAQ Overview - Wolfgang Kühn (Univ. Giessen, II.Physikalisches Institut)

14:00 CBM DAQ Overview - Walter F. J. Müller (FAIR, Darmstadt)

14:20 CBM FPGA-based sub-systems - Christian Pauly (Bergische Universität Wuppertal)
14:45
14:45 - 16:55
Room: KBW small lecture hall
Contributions

14:45 Hardware: Trb3 family - Jan Michel (IKF, Universität Frankfurt)

15:05 Hardware: Fpga crate modules - Pawel Marciniewski (Uppsala University)

15:55 Hardware: AFCK - Wojciech Zabolotny (WUT, Warsaw)

16:25 Discussion: Hardware Projects
16:55
16:55 - 18:25
Room: KBW small lecture hall
Contributions

16:55 SODA optical network - Myroslav Kavatsyuk (KVI, University of Groningen)

17:25 FPGA Network for CBM - Jan Michel (IKF, Universität Frankfurt)

17:55 Discussion: "FairNet" for both experiments?
Friday, 20 February 2015
09:00
09:00 - 09:55
Room: KBW 2.27
Contributions

09:00 FPGA-TDC: Status and Plans - Cahit Ugur (GSI, Darmstadt)

09:25 A low-accuracy TDC? - Jan Michel (IKF, Universität Frankfurt)

09:35 RICH / DIRC front-ends - Michael Traxler (GSI, Darmstadt)
09:55
09:55 - 11:40
Room: KBW 2.27
Contributions

09:55 GBT-FPGA implementation - Adrian Byszuk (WUT, Warsaw)

10:15 Control of ASICS via GBTx - Wojciech Zabolotny (WUT, Warsaw)

10:55 Panda GBT - Matthias Drochner (FZJ)

11:20 CBM ROB Prototype - Jörg Lehnert (GSI, Darmstadt)

11:25 Discussion: GBTx
11:40
11:40 - 12:30
Room: KBW 2.27
Contributions

11:40 Fast Control & Timing (CBM) - Walter F. J. Müller (FAIR, Darmstadt)

12:00 Fast Control & Timing (Panda) - Myroslav Kavatsyuk (KVI, University of Groningen)

12:15 Discussion: Fast Control / Timing
12:30 Lunch
Lunch
12:30 - 13:30
13:30
13:30 - 14:35
Room: KBW 2.27
Contributions

13:30 Data & Control link via GbE - Grzegorz Korcyl (Jagiellonian University)

13:50 FLES Input Interface - Dirk Hutter (FIAS, Frankfurt)

14:05 Ethernet transport protocols - Wojciech Zabolotny (WUT, Warsaw)

14:20 Data transport FPGA to Computer (Panda) - Wolfgang Kühn (Univ. Giessen, II.Physikalisches Institut)
14:40 Close-Out & Further Plans
Close-Out & Further Plans
14:40 - 15:00
Room: KBW 2.27